In high-speed clock recovery integrated circuit design, it is generally applied that passive filter circuit, phase-locked loop (PLL) circuit and synchronous oscillator (SO) circuit. Then, according to the applied different technology and circuit working condition, an appropriate adjustment is taken again.
The advantages of passive filter circuit are simple structure, good frequency phase stability. The disadvantages of passive filter circuit are as follow: it cannot be integrated, working frequency region is narrow, and it cannot be adjusted within a chip.
The advantages of synchronous oscillator circuit are as follow: noise bandwidth without relation with capture range, higher input sensitivity, faster capture speed than second-order PLL and better suppression ability for noise of carrier frequency remote end. The disadvantages of synchronous oscillator circuit are as follow: phase difference cannot be cancelled, phase difference is related with frequency deviation, and noise performance of carrier frequency near end is worse.
The advantages of PLL circuit are as follow: it can be fully integrated in a semiconductor chip, it can trace the change of input data baud-rate, and in a certain condition, the phase-difference can be cancelled. The disadvantages of PLL circuit are as follow: the circuit is rather complex, capture range of itself is rather small, it is difficult to solve conflict of the noise bandwidth and the capture range, and the capture speed is rather slow. Nevertheless, when combing the PLL circuit with other circuits, performance can be improved greatly; therefore, it is one of the main directions of high-speed clock-recovery circuit design.
The injection-locked PLL (ILPLL) circuit, which is an improvement of PLL circuit and SO circuit, includes IL circuit and PLL circuit. FIG. 1 shows a conventional ILPLL circuit block diagram that is consisted of two parts of circuit: IL and PLL. In FIG. 1, inside the dot-line block is the PLL path (path means an uncompleted PLL circuit), and outside the dot-line block is the IL path (path means an uncompleted IL circuit). The PLL path includes a Phase Shifter 11, a Loop Filter 12 and a phase detector 14. The IL path mainly includes a Voltage Control Oscillator (VCO) 13. The input data Vi with phase θi is sent to the input ports of the phase shifter 11 and the VCO 13 simultaneously. The output data of the phase shifter 11 with phase θi+α is sent to the phase detector 14. After processed by the loop filter 12, the output data of the phase detector 14 with phase θe is used as the control signal of the VCO 13. The VCO 13 outputs a clock signal with phase θo, which is also returned to phase detector 14.
The combined circuit of an IL and a PLL, mentioned above, in certain degree, combines the advantages of two circuits and compensates their individual disadvantages. Nevertheless, there are two disadvantages, which affect the implementation in a semiconductor chip. The two disadvantages are:                (1) when a clock frequency is an ultrahigh frequency, there are some difficulties to implement on a chip;        (2) the present circuit cannot better adjust the phase difference between the input data Vi and the output clock.        
In addition, usually the circuit needs to add a double frequency circuit 15 (X2) in front of the output in order to produce a needed clock (Vo). The double frequency circuit brings another phase deviation, which is difficult to control.